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APPLICATION NOTES AND DEVELOPMENT SYSTEM AVAILABLE
AN99 * AN115 * AN124 *AN133 * AN134 * AN135
Single Supply / Low Power / 256-tap / SPI bus
X9271
Single Digitally-Controlled (XDCPTM) Potentiometer
FEATURES * 256 Resistor Taps * SPI Serial Interface for write, read, and transfer operations of the potentiometer * Wiper Resistance, 100 typical @ VCC = 5V * 16 Nonvolatile Data Registers * Nonvolatile Storage of Multiple Wiper Positions * Power On Recall. Loads Saved Wiper Position on Power Up. * Standby Current < 3A Max * VCC: 2.7V to 5.5V Operation * 50K, 100K versions of End to End Resistance * 100 yr. Data Retention * Endurance: 100,000 Data Changes per Bit per Register * 14-Lead TSSOP, 16-Lead CSP (Chip Scale Package) * Low Power CMOS DESCRIPTION The X9271 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four nonvolatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
VCC RH
SPI Bus Interface
Address Data Status
Write Read Transfer Inc/Dec Bus Interface and Control Control
Power On Recall Wiper Counter Register (WCR) Data Registers 16 Bytes
50K and 100K 256-taps POT
VSS
RW
RL
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X9271
DETAILED FUNCTIONAL DIAGRAM
VCC
Bank 0 Power On Recall R0 R1 HOLD CS SCK SO SI A0 A1 WP WIPER COUNTER REGISTER (WCR)
50K and 100K 256-taps
RH
INTERFACE AND CONTROL CIRCUITRY DATA
R2 R3
RL RW
Bank 1 R0 R1
Bank 2 R0 R1
Bank 3 R0 R1
R2 R3 Control
R2 R3
R2 R3
12 additional nonvolatile registers 3 Banks of 4 registers x 8-bits
VSS
CIRCUIT LEVEL APPLICATIONS * Vary the gain of a voltage amplifier * Provide programmable dc reference voltages for comparators and detectors * Control the volume in audio circuits * Trim out the offset voltage error in a voltage amplifier circuit * Set the output voltage of a voltage regulator * Trim the resistance in Wheatstone bridge circuits * Control the gain, characteristic frequency and Q-factor in filter circuits * Set the scale factor and zero point in sensor signal conditioning circuits * Vary the frequency and duty cycle of timer ICs * Vary the dc biasing of a pin diode attenuator in RF circuits * Provide a control variable (I, V, or R) in feedback circuits
SYSTEM LEVEL APPLICATIONS * Adjust the contrast in LCD displays * Control the power level of LED transmitters in communication systems * Set and regulate the DC biasing point in an RF power amplifier in wireless systems * Control the gain in audio and home entertainment systems * Provide the variable DC bias for tuners in RF wireless systems * Set the operating points in temperature control systems * Control the operating point for sensors in industrial systems * Trim offset and gain errors in artificial intelligent systems
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X9271
PIN CONFIGURATION
TSSOP S0 A0 NC CS SCK SI VSS 1 2 3 4 5 6 7 X9271 4 3 2 1
14 13 12 11 10 9 8
VCC RL RH RW HOLD A1 WP D SI VSS WP A1 B C CS SCK SO NC NC RW A A0 VCC RL RH
NC HOLD
PIN ASSIGNMENTS TSSOP
1 2 3 4 5 6 7 8 9 10 11 12 13 14
CSP
B3 A4 B2, C2, C3 B4 C4 D4 D3 D2 D1 C1 B1 A1 A2 A3
Symbol
SO A0 NC CS SCK SI VSS WP A1 HOLD RW RH RL VCC Serial Data Output. Device Address. No Connect. Chip Select. Serial Clock. Serial Data Input. System Ground. Hardware Write Protect. Device Address.
Function
Device select. Pause the serial bus. Wiper Terminal of the Potentiometer. High Terminal of the Potentiometer. Low Terminal of the Potentiometer. System Supply Voltage.
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X9271
PIN DESCRIPTIONS Bus Interface Pins SERIAL OUTPUT (SO) SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. SERIAL INPUT SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. SERIAL CLOCK (SCK) The SCK input is used to clock data into and out of the X9271. HOLD (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. CMOS level input. DEVICE ADDRESS (A1 - A0) The address inputs are used to set the the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9271. CHIP SELECT (CS) When CS is HIGH, the X9271 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9271, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system supply voltage. The VSS pin is the system ground. Other Pins HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. NO CONNECT. No connect pins should be left floating. This pins are used for Xicor manufacturing and testing purposes.
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X9271
PRINCIPLES OF OPERATION Device Description SERIAL INTERFACE The X9271 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. ARRAY DESCRIPTION The X9271 is comprised of a resistor array (see Figure 1). The array contains the equivalent of 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The 8-bits of the WCR (WCR[7:0]) are decoded to select, and enable, one of 256 switches (see Table 1). POWER UP AND DOWN RECOMMENDATIONS. There are no restrictions on the power-up or powerdown conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC VH, VL, VW. The VCC ramp rate specification is always in effect.
Figure 1. Detailed Potentiometer Block Diagram
SERIAL DATA PATH FROM INTERFACE CIRCUITRY REGISTER 0 (DR0) 8
BANK_0 Only
SERIAL BUS INPUT REGISTER 1 (DR1) 8 PARALLEL BUS INPUT C O U N T E R D E C O D E
RH
REGISTER 2 (DR2)
REGISTER 3 (DR3)
WIPER COUNTER REGISTER (WCR) INC/DEC LOGIC
IF WCR = 00[H] THEN RW = RL IF WCR = FF[H] THEN RW = RH
UP/DN MODIFIED SCK
UP/DN CLK RL
RW
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X9271
DEVICE DESCRIPTION Wiper Counter Register (WCR) The X9271 contains a Wiper Counter Register for the DCP potentiometer. The Wiper Counter Register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/ Decrement instruction. Finally, it is loaded with the contents of its Data Register zero (DR0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9271 is powereddown. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Powerup guidelines are recommended to ensure proper loadings of the R0 value into the WCR. The DR0 value of Bank 0 is the default value. Data Registers (DR3-DR0) The potentiometer has four 8-bit nonvolatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Counter Register. All operations changing data in one of the Data Registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Bits [7:0] are used to store one of the 256 wiper positions or data (0 ~255). Status Register (SR) This 1-bit Status Register is used to store the system status. WIP: Write In Progress status bit, read only. - When WIP=1, indicates that high-voltage write cycle is in progress. - When WIP=0, indicates that no high-voltage write cycle is in progress
Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).
WCR7 V (MSB) WCR6 V WCR5 V WCR4 V WCR3 V WCR2 V WCR1 V WCR0 V (LSB)
Table 2. Data Register, DR (8-bit), DR[7:0]: Used to store wiper positions or data (Nonvolatile, NV).
Bit 7 NV MSB Bit 6 NV Bit 5 NV Bit 4 NV Bit 3 NV Bit 2 NV Bit 1 NV Bit 0 NV LSB
Table 3. Status Register, SR (WIP is 1-bit)
WIP (LSB)
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X9271
DEVICE DESCRIPTION Instructions IDENTIFICATION BYTE (ID AND A) The first byte sent to the X9271 from the host, following a CS going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave address are a device type identifier. The ID[3:0] bits is the device id for the X9271; this is fixed as 0101[B] (refer to Table 4). The A1-A0 bits in the ID byte is the internal slave address. The physical device address is defined by the state of the A1-A0 input pins. The slave address is externally specified by the user. The X9271 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9271 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A1-A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. INSTRUCTION BYTE (I[3:0]) The next byte sent to the X9271 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode (I[3:0]). The RB and RA bits point to one of the four Data Registers. P0 is the POT selection; since the X9271 is single POT, the P0=0. The format is shown in Table 5. REGISTER BANK SELECTION (R1, R0, P1, P0) There are 16 registers organized into four banks. Bank 0 is the default bank of registers. Only Bank 0 registers can be used for data register to Wiper Counter Register operations. Table 4. Identification Byte Format
Device Type Identifier Set to 0 for proper operation Internal Slave Address
Banks 1, 2, and 3 are additional banks of registers (12 total) that can be used for SPI write and read operations. The data registers in Banks 1, 2, and 3 cannot be used for direct read/write operations between the Wiper Counter Register. Register Selection (DR0 to DR3) Table Register RB RA Selection
0 0 0
Operations
Data Register Read and Write; Wiper Counter Register Operations Data Register Read and Write; Wiper Counter Register Operations Data Register Read and Write; Wiper Counter Register Operations Data Register Read and Write; Wiper Counter Register Operations
0
1
1
1
0
2
1
1
3
Register Bank Selection (Bank 0 to Bank 3) Table P1
0
Bank P0 Selection
0 0
Operations
Data Register Read and Write; Wiper Counter Register Operations Data Register Read and Write Only Data Register Read and Write Only Data Register Read and Write Only
0 1 1
1 0 1
1 2 3
ID3 0 (MSB)
ID2 1
ID1 0
ID0 1
0
0
A1
A0 (LSB)
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X9271
Table 5. Instruction Byte Format
P1 and P0 are used also for register Bank Selection for SPI Register Write and Read operations Pot Selection (WCR Selection) Set to P0=0 for potentiometer operations
Instruction Opcode
Register Selection
I3 (MSB)
I2
I1
P0
RB
RA
P1
P0 (LSB)
DEVICE DESCRIPTION Instructions Five of the eight instructions are three bytes in length. These instructions are: - Read Wiper Counter Register - read the current wiper position of the potentiometer; - Write Wiper Counter Register - change current wiper position of the potentiometer; - Read Data Register - read the contents of the selected Data Register; - Write Data Register - write a new value to the selected Data Register. - Read Status - This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The basic sequence of the three byte instructions is illustrated in Figure 3. These three-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. The Read Status Register instruction is the only unique format (see Figure 4).
Two instructions require a two-byte sequence to complete (Figure 2). These instructions transfer data between the host and the X9271; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: - XFR Data Register to Wiper Counter Register - This transfers the contents of one specified Data Register to the associated Wiper Counter Register. - XFR Wiper Counter Register to Data Register - This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. The final command is Increment/Decrement (Figure 5 and 6). It is different from the other commands, because it's length is indeterminate. Once the command is issued, the master can clock the selected wiper up and/or down in one resistor segment steps; thereby, providing a fine tuning capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the RL terminal. See Instruction format for more details. Write in Process (WIP bit) The contents of the Data Registers are saved to nonvolatile memory when the CS pin goes from LOW to HIGH after a complete write sequence is received by the device. The progress of this internal write operation can be monitored by a Write In Process bit (WIP). The WIP bit is read with a Read Status command.
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X9271
Figure 2. Two-Byte Instruction Sequence
CS SCK
SI
0
1
0
1
0 0
0 0 A1 A0 I3 I2 I1 I0
0
0
ID3 ID2 ID1 ID0 Device ID
RB RA P1 P0 Register Address Pot/Bank Address
Internal Address
Instruction Opcode
These commands only valid when P1=P0=0
Figure 3. Three-Byte Instruction Sequence (Write)
CS SCL SI 0 0 0 0 A1 A0 Internal Address I3 I2 I1 I0 RB RA P1 P0 Register Address D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
ID3 ID2 ID1 ID0 Device ID
Instruction Opcode
Pot/Bank WCR[7:0] valid only when P1=P0=0; Address or Data Register Bit [7:0] for all values of P1 and P0
Figure 4. Three-Byte Instruction Sequence (Read)
CS SCL SI 0 0 0 0 A1 A0 Internal Address I3 I2 I1 I0 RB RA P1 P0 Register Address Pot/Bank Address
0
1
0
1
X
X
X
X
X
X
X
X
ID3 ID2 ID1 ID0 Device ID
Don't Care
Instruction Opcode
S0 D7 D6 D5 D4 D3 D2 D1 D0 WCR[7:0] valid only when P1=P0=0; or Data Register Bit [7:0] for all values of P1 and P0
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X9271
Figure 5. Increment/Decrement Instruction Sequence
CS SCL SI 0 0 0 0 A1 A0 Internal Address I3 I2 I1 I0 0 0 I N C 1 I N C 2 I N C n D E C 1 D E C n
0
1
0
1
ID3 ID2 ID1 ID0 Device ID
RA RB P1 P0 Register Address Pot/Bank Address
Instruction Opcode
Figure 6. Increment/Decrement Timing Limits
tWRID SCK
SI
V W
VOLTAGE OUT
INC/DEC CMD ISSUED
Table 6. Instruction Set Instruction
Read Wiper Counter Register Write Wiper Counter Register Read Data Register Write Data Register XFR Data Register to Wiper Counter Register XFR Wiper Counter Register to Data Register Increment/Decrement Wiper Counter Register Read Status (WIP bit)
Note: 1/0 = data is one or zero
I3
1 1 1 1 1
I2
0 0 0 1 1
Instruction Set I1 I0 RB RA
0 1 1 0 0 1 0 1 0 1 0 0 1/0 1/0 1/0 0 0 1/0 1/0 1/0
P1
0 0 1/0 1/0 0
P0
1/0 1/0 1/0 1/0 0
Operation
Read the contents of the Wiper Counter Register Write new value to the Wiper Counter Register Read the contents of the Data Register pointed to by P1-P0 and RB-RA Write new value to the Data Register pointed to by P1-P0 and RB-RA Transfer the contents of the Data Register pointed to by RB-RA (Bank 0 only) to the Wiper Counter Register Transfer the contents of the Wiper Counter Register to the Register pointed to by RB-RA (Bank 0 only) Enable Increment/decrement of the Wiper Counter Register Read the status of the internal write cycle, by checking the WIP bit.
1
1
1
0
1/0
1/0
0
0
0 0
0 1
1 0
0 1
0 0
0 0
0 0
0 1
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X9271
INSTRUCTION FORMAT Read Wiper Counter Register (WCR)
Device Type Identifier 1 0 1 Device Addresses Instruction Opcode 0 0 1 DR/Bank Addresses 0 0 0 Wiper Position (Sent by X9271 on SO) W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1
CS Falling Edge 0
0 0 A1 A0 1
W C 0 R 7
CS W Rising C Edge R 0
Write Wiper Counter Register (WCR)
Device Type Identifier 1 0 1 Device Addresses Instruction Opcode 0 1 0 DR/Bank Addresses 0 0 0 W C 0 R 7 Data Byte (Sent by Host on SI) W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1
CS Falling Edge 0
0 0 A1 A0 1
CS W Rising C Edge R 0
Read Data Register (DR)
Device Type Device Instruction DR/Bank Data Byte CS CS Identifier Addresses Opcode Addresses (Sent by X9271 on SO) Falling Rising Edge 0 1 0 1 0 0 A1 A0 1 0 1 1 RB RA P1 P0 D7 D 6 D5 D4 D3 D2 D1 D0 Edge
Write Data Register (DR)
Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Data Byte (Sent by Host on SI) HIGH-VOLTAGE WRITE CYCLE
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CS CS Falling Rising Edge 0 1 0 1 0 0 A1 A0 1 1 0 0 RB RA P1 P0 D7 D 6 D5 D4 D3 D2 D1 D0 Edge
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device Type CS Identifier Falling Edge 0 1 0 1 Device Addresses Instruction Opcode DR/Bank Addresses RB RA 0 0 CS Rising Edge HIGH-VOLTAGE WRITE CYCLE
0 0 A1 A0 1 1 1 0
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X9271
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type Device CS Identifier Addresses Falling Edge 0 1 0 1 0 0 A1 A0 Instruction Opcode DR/Bank Addresses 0 0 CS Rising Edge
1 1 0 1 RB RA
Increment/Decrement Wiper Counter Register (WCR)
Device Type CS Identifier Falling Edge 0 1 0 1 Device Addresses 00 A1 A0 Instruction Opcode DR/Bank Addresses Increment/Decrement (Sent by Master on SDA) . . . . CS Rising I/D I/D Edge
0 0 1 0 X X 0 0 I/D I/D
Read Status Register (SR)
Device Type Device CS Identifier Addresses Falling Edge 0 1 0 1 0 0 A1 A0 Instruction Opcode DR/Bank Addresses Data Byte (Sent by X9271 on SO) WIP CS Rising Edge
010100010000000
Notes: (1) (2) (2) (3) (4)
"A1 ~ A0": stands for the device addresses sent by the master. WCRx refers to wiper position data in the Wiper Counter Register "I": stands for the increment operation, SI held HIGH during active SCK phase (high). "D": stands for the decrement operation, SI held LOW during active SCK phase (high). "X:": Don't Care.
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X9271
ABSOLUTE MAXIMUM RATINGS Temperature under bias ....................-65C to +135C Storage temperature .........................-65C to +150C Voltage on SCK any address input with respect to VSS ..................................-1V to +7V V = |(VH-VL)|...................................................... 5.5V Lead temperature (soldering, 10 seconds)........ 300C IW (10 seconds).................................................. 6mA COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS Temp
Commercial Industrial
Min.
0C -40C
Max.
+70C +85C
Device
X9271 X9271-2.7
Supply Voltage (VCC)(4) Limits
5V 10% 2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended industrial operating conditions unless otherwise stated.) Limits Symbol
RTOTAL RTOTAL
Parameter
End to End Resistance End to End Resistance End to End Resistance Tolerance Power Rating
Min.
Typ.
100 50
Max.
Units
k k
Test Conditions
T version U version
20 50 3 300 150 VSS -120 0.4 1 0.2 300 20 10/10/25 VCC
% mW mA V dBV/ Hz % MI(3) MI(3) ppm/C ppm/C pF See Macro model Rw(n)(actual) - Rw(n)(expected)(5) Rw(n + 1) - [Rw(n) + MI](5) IW = 3mA @ VCC = 3V IW = 3mA @ VCC = 5V VSS = 0V Ref: 1V 25C, each pot
IW RW RW VTERM
Wiper Current Wiper Resistance Wiper Resistance Voltage on any RH or RL Pin Noise Resolution Absolute Linearity(1) Relative Linearity(2) Temperature Coefficient of RTOTAL Ratiometric Temp. Coefficient
CH/CL/CW
Potentiometer Capacitancies
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT / 255 or (RH - RL) / 255, single pot (4) During power up VCC > VH, VL, and VW. (5) n = 0, 1, 2, ...,255; m =0, 1, 2, ...., 254. REV 1.1.7 2/6/03
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X9271
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol
ICC1 ICC2 ISB ILI ILO VIH VIL VOL VOH VOH
Parameter
VCC supply current (active) VCC supply current (nonvolatile write) VCC current (standby) Input leakage current Output leakage current Input HIGH voltage Input LOW voltage Output LOW voltage Output HIGH voltage Output HIGH voltage
Min.
Typ.
Max.
400
Units
A mA A A A V V V V V IOL = 3mA
Test Conditions
fSCK = 2.5 MHz, SO = Open, VCC=6V Other Inputs = VSS fSCK = 2.5MHz, SO = Open, VCC=6V Other Inputs = VSS SCK = SI = VSS, Addr. = VSS, CS = VCC = 6V VIN = VSS to VCC VOUT = VSS to VCC
1
5 3 10 10
VCC x 0.7 -1 VCC - 0.8 VCC - 0.4
VCC + 1 VCC x 0.3 0.4
IOH = -1mA, VCC +3V IOH = -0.4mA, VCC +3V
ENDURANCE AND DATA RETENTION Parameter
Minimum endurance Data retention
Min.
100,000 100
Units
Data changes per bit per register years
CAPACITANCE Symbol
CIN/OUT COUT CIN
(6) (6) (6)
Test
Input / Output capacitance (SI) Output capacitance (SO) Input capacitance (A0, CS, WP, HOLD, and SCK)
Max.
8 8 6
Units
pF pF pF
Test Conditions
VOUT = 0V VOUT = 0V VIN = 0V
POWER-UP TIMING Symbol
tr VCC tPUW
(6)
Parameter
VCC Power-up rate Power-up to initiation of read operation Power-up to initiation of write operation
Min.
0.2
Max.
50 1 50
Units
V/ms ms ms
tPUR(7)
(7)
A.C. TEST CONDITIONS Input Pulse Levels
Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5
Notes: (6) This parameter is not 100% tested (7) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested.
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X9271
EQUIVALENT A.C. LOAD CIRCUIT
SPICE Macromodel RTOTAL RH SO pin 2714 100pF SO pin 1217 100pF 10pF RW CL CW 25pF CL 10pF RL
5V 1462
3V 1382
AC TIMING Symbol
fSCK tCYC tWH tWL tLEAD tLAG tSU tH tRI tFI tDIS tV tHO tRO tFO tHOLD tHSU tHH tHZ tLZ TI tCS tWPASU tWPAH SSI/SPI clock frequency SSI/SPI clock cycle time SSI/SPI clock high time SSI/SPI clock low time Lead time Lag time SI, SCK, HOLD and CS input setup time SI, SCK, HOLD and CS input hold time SI, SCK, HOLD and CS input rise time SI, SCK, HOLD and CS input fall time SO output disable time SO output valid time SO output hold time SO output rise time SO output fall time HOLD time HOLD setup time HOLD hold time HOLD low to output in high Z HOLD high to output in low Z Noise suppression time constant at SI, SCK, HOLD and CS inputs CS deselect time WP, A0 setup time WP, A0 hold time 2 0 0 400 100 100 100 100 10 0 100 100 0 500 200 200 250 250 50 50 2 2 250 200
Parameter
Min.
Max.
2.5
Units
MHz ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns s ns ns
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X9271
HIGH-VOLTAGE WRITE CYCLE TIMING Symbol
tWR
Parameter
High-voltage write cycle time (store instructions)
Typ.
5
Max.
10
Units
ms
XDCP TIMING Symbol
tWRPO tWRL
Parameter
Wiper response time after the third (last) power supply is stable Wiper response time after instruction issued (all load instructions)
Min.
5 5
Max.
10 10
Units
s s
SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance
REV 1.1.7 2/6/03
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Characteristics subject to change without notice.
16 of 23
X9271
TIMING DIAGRAMS Input Timing
tCS CS tLEAD SCK tSU SI MSB tH tWL tCYC ... tWH ... tLAG
tFI LSB
tRI
SO
High Impedance
Output Timing
CS
SCK tV SO MSB tHO
... tDIS ... LSB
SI
ADDR
Hold Timing
CS tHSU SCK ... tRO SO tHZ SI tHOLD HOLD tLZ tFO tHH
REV 1.1.7 2/6/03
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Characteristics subject to change without notice.
17 of 23
X9271
XDCP Timing (for All Load Instructions)
CS
SCK
... tWRL MSB ... LSB
SI
VWx
SO
High Impedance
Write Protect and Device Address Pins Timing
CS tWPASU WP A0 A1
(Any Instruction) tWPAH
REV 1.1.7 2/6/03
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Characteristics subject to change without notice.
18 of 23
X9271
APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers
VR +VR
RW
I Three terminal Potentiometer; Variable voltage divider
Two terminal Variable Resistor; Variable current
Application Circuits Noninverting Amplifier
VS + - VO VIN 317 R1 R2 R1 VO (REG)
Voltage Regulator
Iadj R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Offset Voltage Adjustment
R1 VS 100K - + TL072 10K 10K +12V 10K -12V VO R2
Comparator with Hysterisis
VS - + VO
VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min)
} R1
} R2 19 of 23
REV 1.1.7 2/6/03
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Characteristics subject to change without notice.
X9271
Application Circuits (continued) Attenuator
C VS R1 - VS R3 R4 R1 = R2 = R3 = R4 = 10k R1 + VO R2 R + - VO
Filter
R2
VO = G VS -1/2 G +1/2
GO = 1 + R2/R1 fc = 1/(2RC)
Inverting Amplifier
R1 R2
Equivalent L-R Circuit
}
VS
}
- + VO
C1 VS
R2 + -
VO = G VS G = - R2/R1
ZIN
R1 R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2
Function Generator
C
- +
R2
R1 - +
} RA } RB
frequency R1, R2, C amplitude RA, RB
REV 1.1.7 2/6/03
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Characteristics subject to change without notice.
20 of 23
X9271
PACKAGING INFORMATION
14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.193 (4.9) .200 (5.1)
.047 (1.20)
.0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) Gage Plane 0- 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05)
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1.7 2/6/03
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Characteristics subject to change without notice.
21 of 23
X9271 16-Bump Chip Scale Package (CSP B16) Package Outline Drawing
a d
f
9271TRR YWW I LOT #
A4 B4
A3 B3 C3 D3
A2 B2 C2 D2
A1 B1 C1 D1
b
j m
C4 D4
l
Top View (Marking Side)
k
Side View
e
Bottom View (Bumped Side)
e c
Side View
Package Dimensions
Symbol a b c d e f j k l m Min 2.593 2.771 0.644 0.444 0.200 0.300 Millimeters Nominal 2.623 2.801 0.677 0.457 0.220 0.320 0.5 0.5 0.562 0.651 Max 2.653 2.831 0.710 0.470 0.240 0.340
Ball Matrix:
4 A B C D A0 CS SCK SI 3 Vcc SO NC Vss 2 RL NC NC WP 1 RH RW HOLD A1
Package Width Package Length Package Height Body Thickness Ball Height Ball Diameter Ball Pitch - Width Ball Pitch - Length Ball to Edge Spacing - Width Ball to Edge Spacing - Length
0.537 0.626
0.587 0.676
REV 1.1.7 2/6/03
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Characteristics subject to change without notice.
22 of 23
X9271
ORDERING INFORMATION X9271 Device Y V T V VCC Limits Blank = 5V 10% -2.7 = 2.7 to 5.5V Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C Package V = 14-Lead TSSOP B = 16-Lead CSP Potentiometer Organization Pot U= 50K T= 100K
LIMITED WARRANTY
(c)Xicor, Inc. 2003 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
REV 1.1.7 2/6/03
www.xicor.com
Characteristics subject to change without notice.
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